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? semiconductor components industries, llc, 2008 july, 2008 ? rev. p5 1 publication order number: ncp5395/d ncp5395 product preview 2/3/4-phase controller with on board gate drivers for cpu applications the ncp5395 provides up to a four ? phase buck solution which combines differential voltage sensing, differential phase current sensing, adaptive voltage positioning, and on board gate drivers. dual ? edge pulse ? width modulation (pwm) combined with inductor current sensing reduces system cost by providing the fastest initial response to dynamic load events. dual ? edge multiphase modulation reduces the total bulk and ceramic output capacitance required to meet transient regulation specifications. the on board gate drivers includes adaptive non overlap and power saving operation. a high performance operational error amplifier is provided to simplify compensation of the system. patented dynamic reference injection further simplifies loop compensation by eliminating the need to compromise between closed ? loop transient response and dynamic v id performance. features ? meets intel?s vr11.1 specifications ? meets amd 6 bit code specifications ? dual ? edge pwm for fastest initial response to transient loading ? high performance operational error amplifier ? internal soft start ? dynamic reference injection (patent #us07057381) ? dac range from 0.5 v to 1.6 v ? dac feed forward function (patient pending) ? 0.5% dac voltage accuracy from 1.0 v to 1.6 v ? true differential remote voltage sensing amplifier ? phase ? to ? phase current balancing ? ?lossless? differential inductor current sensing ? differential current sense amplifiers for each phase ? adaptive voltage positioning (avp) ? oscillator frequency range of 125 khz ? 1 mhz ? latched over voltage protection (ovp) ? guaranteed startup into pre ? charged loads ? threshold sensitive enable pin for vtt sensing ? power good output with internal delays ? thermally compensated current monitoring ? thermal shutdown protection ? adaptive ? non ? overlap gate drive circuit ? output disable control turn off of both phase pair mosfets ? this is a pb ? free device applications ? desktop processors this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. http://onsemi.com marking diagram device package shipping ? ordering information qfn48 case 485k plastic NCP5395MNR2G qfn48 (pb ? free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 148 48 ncp5395 awlyywwg 1 a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package cs4p cs4n ilim cs3p cs3n cs2p cs2n cs1p cs1n en vrrdy g4 bg1 agnd down ? bonded to exposed flag rosc vid7/amd vid6 vid5 vid4 vid3 vid2 vid1 vid0 psi bg3 bst1 tg1 swn1 vccp bg2 swn2 tg2 bst2 drvon swn3 tg3 vbst3 1 48 vcc gnd dac cssum vdfb vdrp vfb comp diffout vsn vsp imon
ncp5395 http://onsemi.com 2 figure 1. ncp5395 functional block diagram gnd (flag) uvlo 4.25 v oscillator flexible dac overvoltage protection diff amp error amp 1.3 v gain = 6 gain = 6 gain = 6 gain = 6 + + + + + i limit control, fault logic and monitor circuits phase 1 gate driver with adaptive non ? overlap phase 2 gate driver with adaptive non ? overlap phase 3 gate driver with adaptive non ? overlap vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7/amd psi vsn vsp diffout vfb comp vdrp vdfb cssum cs1p cs1n cs2p cs2n cs3p cs3n cs4p cs4n rosc ilim en vcc vccp bst1 tg1 swn1 bg1 bst2 tg2 swn2 bg2 bst3 tg3 swn3 bg3 g4 imon drvon vr_rdy + - - + - + - + - + - + - + - + - + - + - + + - - + - + dac
ncp5395 http://onsemi.com 3 figure 2. typical 2 phase application pwm1_sense_p 12v_filter 12v_filter pwm1_sense_n 2 1 d g s imon d g s d g s pwm3_sense_p 12v_filter pwm3_sense_n c17 r47 r137 vccp r14 rdrp7 2.61k rfb6 rlim7 cdfb3 12v_filter cf3 riso7 c31 r226 c82 c32 ch3 cfb4 rf3 rdfb3 rt8 riso8 r24 48l 7x7 qfn ncp5395 vid4 7 swn3 46 vid0 3 vid1 4 vid2 5 vid3 6 imon 13 vr_rdy 34 psi 2 cs2p 29 bg3 1 vsp 14 comp 17 cs3p 27 cs3n 28 bg1 36 en 33 cs1n 32 cs1p 31 cs2n 30 vid7 10 dac 22 cssum 21 vcc 24 gnd 23 cs4n 26 cs4p 25 vfb 18 rosc 11 diffout 16 g4 35 vid5 8 vid6 9 vsn 15 vbst3 48 tg1 38 bg2 41 bst1 37 ilim 12 vdrp 19 vdfb 20 vccp 40 swn1 39 swn2 42 tg2 43 bst2 44 drvon 45 tg3 47 rfb7 r28 r139 rlim8 vccp vtt +5.0v pwm1_sense_p enable pwm3_sense_p vid0 vid7 vid3 drvon vid5 vid1 vid6 vid2 vid4 vtt pwm1_sense_n pwm3_sense_n psi#_cpu c34 d g s d g s d g s 21 flag = gnd
ncp5395 http://onsemi.com 4 figure 3. typical 3 phase application 12v_filter 12v_filter pwm1_sense_p pwm1_sense_n 2 1 d g s d g s d g 12v_filter pwm3_sense_n pwm3_sense_p c37 r46 r145 vccp 12v_filter r29 rdrp10 2.61k rfb8 c38 rlim9 cdfb4 cf4 12v_filter riso4 c40 r236 c83 c41 ch4 cfb5 r32 rf4 rdfb4 rt10 riso10 r33 2 1 48l 7x7 qfn ncp5395 vid4 7 swn3 46 vid0 3 vid1 4 vid2 5 vid3 6 imon 13 vr_rdy 34 psi 2 cs2p 29 bg3 1 vsp 14 comp 17 cs3p 27 cs3n 28 bg1 36 en 33 cs1n 32 cs1p 31 cs2n 30 vid7 10 dac 22 cssum 21 vcc 24 gnd 23 cs4n 26 cs4p 25 vfb 18 rosc 11 diffout 16 g4 35 vid5 8 vid6 9 vsn 15 vbst3 48 tg1 38 bg2 41 bst1 37 ilim 12 vdrp 19 vdfb 20 vccp 40 swn1 39 swn2 42 tg2 43 bst2 44 drvon 45 tg3 47 d g s rfb10 d g s d g s r34 pwm2_sense_p 12v_filter pwm2_sense_n r148 rlim11 +5.0v vccp enable vtt pwm1_sense_p pwm3_sense_p pwm2_sense_p vid0 vid7 vid3 drvon vid5 vid1 vid6 vid2 vid4 vtt pwm2_sense_n pwm1_sense_n pwm3_sense_n psi#_cpu c48 d g s d g s d g s 21 flag = gnd s
ncp5395 http://onsemi.com 5 vid0 vid7 vid6 vid2 vid4 vid3 vid5 figure 4. typical 4 phase application 12v_filter pwm1_sense_p 12v_filter pwm1_sense_n 2 1 d g s imon d g s d g s pwm3_sense_p 12v_filter pwm3_sense_n d g s 12v_filter ncp5359 vcc 4 od 3 in 2 pgnd 6 drl 5 sw 7 drh 8 bst 1 2 1 d g s d g s vccp drvon pwm4_gate 12v_filter rdrp11 rfb9 rlim10 cdfb5 cf5 12v_filter pwm4_sense_p riso11 pwm4_sense_n ch5 cfb6 rf5 rdfb5 rt12 riso12 21 flag = gnd ncp5395 vid4 7 swn3 46 vid0 3 vid1 4 vid2 5 vid3 6 imon 13 vr_rdy 34 psi 2 cs2p 29 bg3 1 vsp 14 comp 17 cs3p 27 cs3n 28 bg1 36 en 33 cs1n 32 cs1p 31 cs2n 30 vid7 10 dac 22 cssum 21 vcc 24 gnd 23 cs4n 26 cs4p 25 vfb 18 rosc 11 diffout 16 g4 35 vid5 8 vid6 9 vsn 15 vbst3 48 tg1 38 bg2 41 bst1 37 ilim 12 vdrp 19 vdfb 20 vccp 40 swn1 39 swn2 42 tg2 43 bst2 44 drvon 45 tg3 47 d g s rfb11 d g s d g s 12v_filter pwm2_sense_n pwm2_sense_p rlim12 vccp +5.0v enable vtt pwm2_sense_p pwm1_sense_p pwm3_sense_p drvon vid1 vtt pwm4_gate pwm1_sense_n pwm4_sense_p pwm3_sense_n pwm2_sense_n pwm4_sense_n psi#_cpu d g s d g s d g s 21 48l 7x7 qfn
ncp5395 http://onsemi.com 6 table 1. pin descriptions pin no. symbol description 1 bg3 low side gate drive #3 2 psi selects dac decode. 3 vid0 voltage id dac input 4 vid1 voltage id dac input 5 vid2 voltage id dac input 6 vid3 voltage id dac input 7 vid4 voltage id dac input 8 vid5 voltage id dac input 9 vid6 voltage id dac input 10 vid7/amd voltage id dac input. pull to v cc (5 v) to enable amd 6 ? bit dac code. 11 rosc a resistance from this pin to ground programs the oscillator frequency and provides a 2 v reference for programming the ilim voltage. 12 ilim over current shutdown threshold setting. ilim = vdrp ? 1.3 v. resistor divide rosc to set threshold 13 imon 0 to 1 volt analog signal proportional to the output load current. vsn referenced clamped to 1.1 vmax 14 vsp non ? inverting input to the internal differential remote sense amplifier 15 vsn inverting input to the internal differential remote sense amplifier 16 diffout output of the differential remote sense amplifier 17 comp output of the compensation amplifier 18 vfb compensation amplifier voltage feedback 19 vdrp voltage output signal proportional to current used for current limit and output voltage droop 20 vdfb droop amplifier voltage feedback 21 cssum inverted sum of the differential current sense inputs 22 dac dac output used to provide feed forward for dynamic vid 23 gnd ground 24 vcc power for the internal control circuits with uvlo monitor 25 cs4p non ? inverting input to current sense amplifier #4 26 cs4n inverting input to current sense amplifier #4 27 cs3p non ? inverting input to current sense amplifier #3 28 cs3n inverting input to current sense amplifier #3 29 cs2p non ? inverting input to current sense amplifier #2 30 cs2n inverting input to current sense amplifier #2 31 cs1p non ? inverting input to current sense amplifier #1 32 cs1n inverting input to current sense amplifier #1 33 en threshold sensitive input. high = startup, low =shutdown. 34 vr_rdy open collector output. high indicates that the output is regulating 35 g4 pwm output pulse to gate driver. 36 bg1 low side gate drive #1 37 bst1 upper mosfet floating bootstrap supply for driver#1 38 tg1 high side gate drive #1 39 swn1 switch node #1 40 vccp power v cc for gate drivers with uvlo monitor 41 bg2 low side gate drive #2 42 swn2 switch node #2 43 tg2 high side gate drive #2 44 bst2 upper mosfet floating bootstrap supply for driver#2 45 drvon bidirectional gate drive enable 46 swn3 switch node #3 47 tg3 high side gate drive #3 48 bst3 upper mosfet floating bootstrap supply for driver#3 flag gnd power supply return (qfn flag)
ncp5395 http://onsemi.com 7 absolute maximum ratings rating symbol value unit electrical information controller power supply voltages to gnd v cc ? 0.3, 7 v driver power supply voltages to gnd v ccp ? 0.3, 15 v high ? side gate driver supplies: bstx to swnx v bst ? v swn 35 v wrt/gnd 40 v 50 ns wrt/gnd ? 0.3, 15 wrt/swn v high ? side fet gate driver voltages: tgx to swnx v tg ? v swn boot + 0.3 v 35 v 50 ns wrt/gnd ? 0.3, 15 wrt/swn ? 2 v (200 ns) v switch node: swnx v swn 35 40 v 50 ns wrt/gnd ? 5 vdc ? 10 v (200 ns) v low ? side gate drive: bgx v bg ? agnd v cc + 0.3 v ? 0.3 vdc (200 ns) v logic inputs v logic ? 0.3, 6 v gnd v gnd 0 v v ? gnd 300 mv imon out v imon 1.1 v all other pins ? 0.3, 5.5 v thermal information thermal characteristic qfn package (note 1) r ja tbd c/w operating junction temperature range (note 2) t j 0 to 125 c operating ambient temperature range t amb 0 to +70 c maximum storage temperature range t stg ? 55 to +150 c moisture sensitivity level qfn package msl 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *all signals referenced to gnd unless noted otherwise. *the maximum package power dissipation must be observed. 1. jesd 51 ? 5 (1s2p direct ? attach method) with 0 lfm 2. operation at ? 40 c to 0 c guaranteed by design, not production tested.
ncp5395 http://onsemi.com 8 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter test conditions min typ max unit error amplifier input bias current ? 200 ? 200 na open loop dc gain c l = 60 pf to gnd, r l = 10 k to gnd ? 100 ? db open loop unity gain bandwidth c l = 60 pf to gnd, r l = 10 k to gnd ? 18 ? mhz open loop phase margin c l = 60 pf to gnd, r l = 10 k to gnd ? 70 ? slew rate v in = 100 mv, g = ? 10v/v, v out = 1.5 v ? 2.5 v, c l = 60 pf to gnd, dc load = 125 a to gnd ? 10 ? v/ s maximum output voltage 10 mv of overdrive, i source = 2.0 ma 3.0 ? ? v minimum output voltage 10 mv of overdrive, i sink = 500 a ? ? 75 mv output source current 10 mv of overdrive, v out = 3.5 v 1.5 2.0 ? ma output sink current 10 mv of overdrive, v out = 0.1 v 0.75 1.0 ? ma differential summing amplifier v+ input pull down resistance drvon = low drvon = high ? ? 0.6 6.0 ? ? k v+ input bias voltage drvon = low drvon = high ? ? 0.5 0.86 ? ? v input voltage range (note 4) ? 0.3 ? 3.0 v ? 3 db bandwidth c l = 80 pf to gnd, r l = 10 k to gnd ? 15 ? mhz closed loop dc gain vs to diffout (note 4) vs+ to vs ? = 0.5 v to 1.6 v 0.98 1.0 1.02 v/v maximum output voltage 10 mv of overdrive, i source = 2 ma 3.0 ? ? v minimum output voltage 10 mv of overdrive, i sink = 1 ma ? ? 0.5 v output source current 10 mv of overdrive, v out = 3 v 1.5 2.0 ? ma output sink current 10 mv of overdrive, v out = 0.2 v 1.0 1.5 ? ma internal offset voltage offset voltage to the (+) pin of the error amp & the vdrp pin ? 2 0 +2 mv 3. design guaranteed. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram. 5. guaranteed by design; not tested in production. 6. internal dac voltage is centered 19 mv below the listed voltage. for vr11.1/vr11.0/vr10 7. no dac offset is implemented for amd operation.
ncp5395 http://onsemi.com 9 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions vdroop amplifier input bias current ? 200 ? 200 na inverting voltage range 0 1.3 3.0 v open loop dc gain c l = 20 pf to gnd including esd r l = 1 k to gnd ? 100 ? db open loop unity gain bandwidth c l = 20 pf to gnd including esd r l = 1 k to gnd ? 18 ? mhz open loop phase margin c l = 20 pf to gnd including esd r l = 1 k to gnd ? 70 ? slew rate c l = 20 pf to gnd including esd r l = 1 k to gnd ? 10 ? v/ s maximum output voltage 10 mv of overdrive, i source = 4.0 ma 3.0 ? ? v minimum output voltage 10 mv of overdrive, i sink = 1.0 ma ? ? 1.0 v output source current 10 mv of overdrive, v out = 3.0 v 4.0 ? ? ma output sink current 10 mv of overdrive, v out = 1.0 v 1.0 ? ? ma cssum amplifier current sense input to cssum gain ? 75 mv < cs < 75 mv ? 3.793 ? 3.70 ? 3.608 v/v current sense input to v drp ? 3 db bandwidth c l = 10 pf to gnd, r l = 10 k to gnd ? 12 ? mhz current summing amp output offset voltage csx ? csnx = 0, csx = 1 v ? 8.0 ? +8.0 mv maximum cssum output voltage csx ? csxn = ? 0.2 v (all phases) i source = 1 ma 3.0 ? ? v minimum cssum output voltage csx ? csxn = 0.7 v (all phases) i sink = 1 ma ? ? 0.3 v output source current v out = 3.0 v 1.0 ? ? ma output sink current v out = 0.3 v 4.0 ? ? ma psi enable high input leakage current external 1k pull ? up to 3.3 v ? ? 1.0 a threshold 450 600 770 mv delay ? 100 ? ns drvon output high voltage sourcing 500 a 3.0 ? ? v output low voltage sinking 500 a ? ? 0.7 v delay time propagation delays ? 10 ? ns rise time c l (pcb) = 20 pf, vo = 10% to 90% ? 10 ? ns fall time c l (pcb) = 20 pf, vo = 10% to 90% ? 10 ? ns internal pull ? down resistance 35 70 140 k v cc voltage when drvon output valid ? ? 2.0 v 3. design guaranteed. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram. 5. guaranteed by design; not tested in production. 6. internal dac voltage is centered 19 mv below the listed voltage. for vr11.1/vr11.0/vr10 7. no dac offset is implemented for amd operation.
ncp5395 http://onsemi.com 10 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions current sense amplifiers input bias current csx = csxn = 1.4 v ? 50 ? 50 na common mode input voltage range ? 0.3 ? 2.0 v differential mode input voltage range ? 120 ? 120 mv current sharing output voltage csx = csxn = 1.00 v, ? tbd ? tbd mv current sense input to pwm gain 0 v < csx ? csxn < 0.1 v, 5.4 5.7 6.0 v/v current sense input to cssum gain 0 v < csx ? csxn < 0.1 v ? 3.793 ? 3.7 ? 3.608 v/v imon v drp to imon gain 1.325 v > v drp > 1.75 v 1.89 2.0 2.02 v/v current sense input to v drp ? 3 db bandwidth c l = 30 pf to gnd, r l = 100 k to gnd ? 4.0 ? mhz v drp to imon output slew rate c l = 30 pf to gnd, load = 100k to gnd ? tbd ? v/ s output referred offset voltage v drp = 1.5 v, i source = 0 ma ? tbd ? tbd mv minimum output voltage v drp = 1.3 v, i sink = 25 a ? ? 0.1 v maximum output voltage i out = 300 a 1.0 ? ? v output sink current v out = 0.3 v 175 ? ? a maximum clamp voltage imon ? vsn v drp = high r load = open 1.1 ? 1.15 v oscillator switching frequency range 100 ? 1100 khz switching frequency accuracy 200 khz < f sw < 600 khz ? ? 5.0 % switching frequency accuracy 100 khz < f sw < 1 mhz ? ? 10 % switching frequency accuracy (2ph or 4ph) r osc = 69.8k tbd ? tbd khz r osc = 16.2k 475 ? 525 r osc = 7.5k tbd ? tbd switching frequency accuracy (3ph) r osc = 69.8k tbd ? tbd khz r osc = 16.2k 494 ? 546 r osc = 7.5k tbd ? tbd rosc output voltage 1.93 2.00 2.05 v modulators (pwm comparators) minimum pulse width fsw = 800 khz ? 30 ? ns magnitude of the pwm ramp tbd 1.0 tbd v 0% duty cycle comp voltage when the pwm outputs remain lo tbd 150 tbd mv 100% duty cycle comp voltage when the pwm outputs remain hi ? 1.15 ? v pwm phase angle error between adjacent phases ? tbd ? tbd vr_rdy (power good) output vr_rdy output saturation voltage i pgd = 10 ma ? ? 0.4 v 3. design guaranteed. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram. 5. guaranteed by design; not tested in production. 6. internal dac voltage is centered 19 mv below the listed voltage. for vr11.1/vr11.0/vr10 7. no dac offset is implemented for amd operation.
ncp5395 http://onsemi.com 11 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions vr_rdy (power good) output vr_rdy rise time external pull ? up of 1 k to 1.25 v, c tot = 45 pf, vo = 10% to 90% ? 100 150 ns vr_rdy output voltage at power ? up vr_rdy pulled up to 5 v via 2 k , t r(vcc) 3 x t r(5v) 100 s t r(vcc) 20 ms ? ? 1.0 v vr_rdy high ? output leakage current vr_rdy = 5.5 v via 1 k ? ? 0.1 a vr_rdy upper threshold voltage (intel) vcore increasing, dac = 1.3 v ? 300 250 mv (below dac) vr_rdy lower threshold voltage (intel) vcore decreasing, dac = 1.3 v 390 350 300 mv (below dac) vr_rdy lower threshold voltage (amd) vcore increasing, dac = 1.3 v ? tbd tbd mv (below dac) vr_rdy lower threshold voltage (amd) vcore decreasing, dac = 1.3 v tbd tbd tbd mv (below dac) vr_rdy rising delay vcore increasing ? tbd ? s vr_rdy falling delay vcore decreasing ? 5.0 ? s pwm g4 output output high voltage sourcing 500 a 3.0 ? ? v mid output voltage 1.4 1.5 1.6 output low voltage sinking 500 a ? ? 0.7 v delay + rise time c l (pcb) = 50 pf, vo = v cc to gnd ? 10 15 ns delay + fall time c l (pcb) = 50 pf, vo = gnd to v cc ? 10 15 ns tri ? state output leakage gx = 2.5 v, x = 1 ? 4 ? ? 1.5 a output impedance ? hi or lo state max resistance to v cc (hi) or gnd (lo) ? 75 150 minimum v cc for valid pwm output level ? ? 2.0 v pwm 4 2/3/4 phase detection 2 phase mode note gate 4 tied to v cc 3.2 ? v cc v 4 phase mode note gate driver will pull to 1.5 v 1.2 ? 2.8 v 3 phase mode note gate 4 tied to gnd 0 ? 0.8 v digital soft ? start soft ? start ramp time dac = 0 to dac = 1.1 v 1.0 ? 1.3 ms vr11 v boot time not used in legacy startup 400 500 600 s vid7/vr11/amd/legacy input vid threshold 450 600 770 mv vr11 input bias current ? 100 ? 100 na 3. design guaranteed. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram. 5. guaranteed by design; not tested in production. 6. internal dac voltage is centered 19 mv below the listed voltage. for vr11.1/vr11.0/vr10 7. no dac offset is implemented for amd operation.
ncp5395 http://onsemi.com 12 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions vid7/vr11/amd/legacy input delay before latching vid change (vid deskewing) measured from the edge of the 1st vid change 200 ? 300 ns amd upper threshold note: when above this threshold the controller will ramp directly to vid without stopping at v boot ? ? 2.9 v amd lower threshold 2.4 ? ? v enable input enable high input leakage current pull ? up to 1.3 v ? ? 200 na vr11.1 threshold 450 600 770 mv amd upper threshold ? 1.3 1.5 v amd lower threshold 0.9 1.1 ? v amd total hysteresis rising ? falling threshold ? 200 ? mv enable delay time measure time from enable transitioning hi to when ss begins ? 3.5 ? ms current limit ilim to vdrp gain 0.99 1.00 1.01 v/v ilim to vrdp gain in psi 4 phase ? 0.25 ? v/v ilim to vdrp gain in psi 3 phase ? 0.333 ? v/v ilim to vdrp gain in psi 2 phase ? 0.5 ? v/v ilim pin input bias current ? 0.1 1.0 a ilim pin working voltage range 0.1 ? 2.0 v ilim accuracy measured with respect to the ilim setting ? 10 ? 10 mv delay ? ? 120 ns overvoltage protection vr11 over voltage threshold dac+ 160 dac+ 190 dac+ 210 mv amd over voltage threshold dac+ 210 dac+ 235 dac+ 260 mv delay ? ? 100 ns undervoltage protection v cc uvlo start threshold 4.0 4.25 4.5 v v cc uvlo stop threshold 3.8 4.05 4.3 v v cc uvlo hysteresis ? 200 ? mv dac output dac output variation i source = 200 a, all vids ? 3.0 0 3.0 % dac output variation i sink = 200 a, all vids ? 3.0 0 3.0 % output source current v out = 1.6 v 0 ? 5.0 ma output sink current v out = 0.3 v 5.0 ? 16 ma 3. design guaranteed. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram. 5. guaranteed by design; not tested in production. 6. internal dac voltage is centered 19 mv below the listed voltage. for vr11.1/vr11.0/vr10 7. no dac offset is implemented for amd operation.
ncp5395 http://onsemi.com 13 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions vid inputs threshold 450 600 770 mv vr11 mode leakage ? 100 ? 100 na amd mode input bias current 10 ? 25 a delay before latching vid change (vid deskewing) measured from the edge of the 1 st vid change 200 ? 300 ns delay before responding to invalid or shutdown codes (remove spec) note: dac must hold the last valid vid during this period ? ? ? s digital dac slew rate limiter slew rate limit (intel mode) 12.5 ? 15 mv/ s slew rate limit (amd mode) 3.125 ? 3.75 mv/ s soft ? start slew rate ? 0.84 ? mv/ s input supply current v cc operating current en low, no pwm 20 ? 40 ma phase shedding cs referred ph shed bias cs2 through cs4 ? 66 ? mv v ccp supply voltage v ccp uvlo start threshold 8.2 9.0 9.5 v v ccp uvlo stop threshold 7.2 8.0 8.5 v v ccp uvlo hysteresis ? 1.0 ? v v ccp por voltage at which the driver ovp becomes active tbd 3.2 tbd boost pin uvlo boost v cc uvlo start threshold 3.5 4.0 v boost v cc uvlo stop threshold 3.3 3.8 v boost v cc uvlo hysteresis 200 mv boost supply current i vccp_norm quiescent supply current in normal operation en = v cc , pwm = osc, f sw = 100k, c load = 0 p, v ccp = 12 v ? ? 42 ma i vcc_sbc standby current en = gnd; no switching, v ccp = 12 v 20 ? 40 ma i bst1 quiescent supply current in normal operation in = v ccp , v ccp = 12 v ? 10 tbd ma i bst2 quiescent supply current in normal operation in = gnd, v ccp = 12 v ? 10 tbd ma i bst3 quiescent supply current in normal operation in = gnd, v ccp = 12 v ? 10 tbd i bst1_sd standby current in = v ccp , v ccp = 12 v ? 0.25 ? ma i bst2_sd standby current in = gnd, v ccp = 12 v ? 0.25 ? ma i bst3_sd standby current in = gnd, v ccp = 12 v ? 0.25 ? ma startup high side short trip (active only during 1 st power on) v swx output overvoltage trip threshold at startup power startup time, v cc > 9 v 1.75 ? 2.0 v 3. design guaranteed. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram. 5. guaranteed by design; not tested in production. 6. internal dac voltage is centered 19 mv below the listed voltage. for vr11.1/vr11.0/vr10 7. no dac offset is implemented for amd operation.
ncp5395 http://onsemi.com 14 electrical characteristics 0 c < t a < 70 c; 0 c < t j < 125 c; 4.75 < v cc < 5.25 v; all dac codes; c vcc = 0.1 f unless otherwise noted. parameter unit max typ min test conditions high side driver r h_tg output resistance, sourcing v bst ? v sw = 12 v ? 1.8 4.2 r h_tg output resistance, sinking v bst ? v sw = 12 v ? 1.0 2.2 tr drvh transition time c load = 3 nf, v bst ? v sw = 12 v ? 16 ? ns tf drvh transition time c load = 3 nf, v bst ? v sw = 12 v ? 11 ? ns tpdh drvh propagation delay (note 4) driving high, c load = 3 nf, v ccp = 12 v ? 20 ? ns tpdh drvh propagation delay (note 4) driving low, c load = 3 nf, v ccp = 12 v ? 20 ? ns low side driver r h_bg output resistance, sourcing sw = gnd ? tbd 4.2 r l_bg output resistance, sinking sw = v cc ? tbd 2.2 tr drvh transition time c load = 3 nf ? 16 ? ns tf drvh transition time c load = 3 nf ? 11 ? ns tpdh drvh propagation delay (note 4) driving high, c load = 3 nf, v ccp = 12 v ? 20 ? ns tpdh drvh propagation delay (note 4) driving low, c load = 3 nf, v ccp = 12 v ? 20 ? ns v ncdt negative current detector threshold (note 3) ? ? 1.0 ? mv thermal shutdown tsd thermal shutdown (note 3) 150 170 ? c tsdhys thermal shutdown hysteresis (note 3) ? 20 ? c vrm 11 dac system voltage accuracy 1.0 v < dac < 1.6 v 0.8 v < dac < 1.0 v 0.5 v < dac < 0.8 v ? ? ? ? ? ? 0.5 5.0 8.0 % mv mv 3. design guaranteed. 4. for propagation delays, ?tpdh? refers to the specified signal going high ?tpdl? refers to it going low. reference gate timing diagram. 5. guaranteed by design; not tested in production. 6. internal dac voltage is centered 19 mv below the listed voltage. for vr11.1/vr11.0/vr10 7. no dac offset is implemented for amd operation.
ncp5395 http://onsemi.com 15 figure 5. timing diagram tpdl drvl tf drvl tpdh drvh th drvh tpdl drvh tf drvh tr drvl tpdh drvl in drvl drvh ? sw sw 90% 2v 90% 90% 90% 10% 10% 10% 2v 10%
ncp5395 http://onsemi.com 16 table 2. vrm11 v id codes v id7 800 mv v id6 400 mv v id5 200 mv v id4 100 mv v id3 50 mv v id2 25 mv v id1 12.5 mv v id0 6.25 mv voltage (v) hex 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 01 0 0 0 0 0 0 1 0 1.60000 02 0 0 0 0 0 0 1 1 1.59375 03 0 0 0 0 0 1 0 0 1.58750 04 0 0 0 0 0 1 0 1 1.58125 05 0 0 0 0 0 1 1 0 1.57500 06 0 0 0 0 0 1 1 1 1.56875 07 0 0 0 0 1 0 0 0 1.56250 08 0 0 0 0 1 0 0 1 1.55625 09 0 0 0 0 1 0 1 0 1.55000 0a 0 0 0 0 1 0 1 1 1.54375 0b 0 0 0 0 1 1 0 0 1.53750 0c 0 0 0 0 1 1 0 1 1.53125 0d 0 0 0 0 1 1 1 0 1.52500 0e 0 0 0 0 1 1 1 1 1.51875 0f 0 0 0 1 0 0 0 0 1.51250 10 0 0 0 1 0 0 0 1 1.50625 11 0 0 0 1 0 0 1 0 1.50000 12 0 0 0 1 0 0 1 1 1.49375 13 0 0 0 1 0 1 0 0 1.48750 14 0 0 0 1 0 1 0 1 1.48125 15 0 0 0 1 0 1 1 0 1.47500 16 0 0 0 1 0 1 1 1 1.46875 17 0 0 0 1 1 0 0 0 1.46250 18 0 0 0 1 1 0 0 1 1.45625 19 0 0 0 1 1 0 1 0 1.45000 1a 0 0 0 1 1 0 1 1 1.44375 1b 0 0 0 1 1 1 0 0 1.43750 1c 0 0 0 1 1 1 0 1 1.43125 1d 0 0 0 1 1 1 1 0 1.42500 1e 0 0 0 1 1 1 1 1 1.41875 1f 0 0 1 0 0 0 0 0 1.41250 20 0 0 1 0 0 0 0 1 1.40625 21 0 0 1 0 0 0 1 0 1.40000 22 0 0 1 0 0 0 1 1 1.39375 23 0 0 1 0 0 1 0 0 1.38750 24 0 0 1 0 0 1 0 1 1.38125 25 0 0 1 0 0 1 1 0 1.37500 26 0 0 1 0 0 1 1 1 1.36875 27 0 0 1 0 1 0 0 0 1.36250 28 0 0 1 0 1 0 0 1 1.35625 29 0 0 1 0 1 0 1 0 1.35000 2a 0 0 1 0 1 0 1 1 1.34375 2b 0 0 1 0 1 1 0 0 1.33750 2c 0 0 1 0 1 1 0 1 1.33125 2d
ncp5395 http://onsemi.com 17 table 2. vrm11 v id codes v id7 800 mv hex voltage (v) v id0 6.25 mv v id1 12.5 mv v id2 25 mv v id3 50 mv v id4 100 mv v id5 200 mv v id6 400 mv 0 0 1 0 1 1 1 0 1.32500 2e 0 0 1 0 1 1 1 1 1.31875 2f 0 0 1 1 0 0 0 0 1.31250 30 0 0 1 1 0 0 0 1 1.30625 31 0 0 1 1 0 0 1 0 1.30000 32 0 0 1 1 0 0 1 1 1.29375 33 0 0 1 1 0 1 0 0 1.28750 34 0 0 1 1 0 1 0 1 1.28125 35 0 0 1 1 0 1 1 0 1.27500 36 0 0 1 1 0 1 1 1 1.26875 37 0 0 1 1 1 0 0 0 1.26250 38 0 0 1 1 1 0 0 1 1.25625 39 0 0 1 1 1 0 1 0 1.25000 3a 0 0 1 1 1 0 1 1 1.24375 3b 0 0 1 1 1 1 0 0 1.23750 3c 0 0 1 1 1 1 0 1 1.23125 3d 0 0 1 1 1 1 1 0 1.22500 3e 0 0 1 1 1 1 1 1 1.21875 3f 0 1 0 0 0 0 0 0 1.21250 40 0 1 0 0 0 0 0 1 1.20625 41 0 1 0 0 0 0 1 0 1.20000 42 0 1 0 0 0 0 1 1 1.19375 43 0 1 0 0 0 1 0 0 1.18750 44 0 1 0 0 0 1 0 1 1.18125 45 0 1 0 0 0 1 1 0 1.17500 46 0 1 0 0 0 1 1 1 1.16875 47 0 1 0 0 1 0 0 0 1.16250 48 0 1 0 0 1 0 0 1 1.15625 49 0 1 0 0 1 0 1 0 1.15000 4a 0 1 0 0 1 0 1 1 1.14375 4b 0 1 0 0 1 1 0 0 1.13750 4c 0 1 0 0 1 1 0 1 1.13125 4d 0 1 0 0 1 1 1 0 1.12500 4e 0 1 0 0 1 1 1 1 1.11875 4f 0 1 0 1 0 0 0 0 1.11250 50 0 1 0 1 0 0 0 1 1.10625 51 0 1 0 1 0 0 1 0 1.10000 52 0 1 0 1 0 0 1 1 1.09375 53 0 1 0 1 0 1 0 0 1.08750 54 0 1 0 1 0 1 0 1 1.08125 55 0 1 0 1 0 1 1 0 1.07500 56 0 1 0 1 0 1 1 1 1.06875 57 0 1 0 1 1 0 0 0 1.06250 58 0 1 0 1 1 0 0 1 1.05625 59 0 1 0 1 1 0 1 0 1.05000 5a 0 1 0 1 1 0 1 1 1.04375 5b
ncp5395 http://onsemi.com 18 table 2. vrm11 v id codes v id7 800 mv hex voltage (v) v id0 6.25 mv v id1 12.5 mv v id2 25 mv v id3 50 mv v id4 100 mv v id5 200 mv v id6 400 mv 0 1 0 1 1 1 0 0 1.03750 5c 0 1 0 1 1 1 0 1 1.03125 5d 0 1 0 1 1 1 1 0 1.02500 5e 0 1 0 1 1 1 1 1 1.01875 5f 0 1 1 0 0 0 0 0 1.01250 60 0 1 1 0 0 0 0 1 1.00625 61 0 1 1 0 0 0 1 0 1.00000 62 0 1 1 0 0 0 1 1 0.99375 63 0 1 1 0 0 1 0 0 0.98750 64 0 1 1 0 0 1 0 1 0.98125 65 0 1 1 0 0 1 1 0 0.97500 66 0 1 1 0 0 1 1 1 0.96875 67 0 1 1 0 1 0 0 0 0.96250 68 0 1 1 0 1 0 0 1 0.95625 69 0 1 1 0 1 0 1 0 0.95000 6a 0 1 1 0 1 0 1 1 0.94375 6b 0 1 1 0 1 1 0 0 0.93750 6c 0 1 1 0 1 1 0 1 0.93125 6d 0 1 1 0 1 1 1 0 0.92500 6e 0 1 1 0 1 1 1 1 0.91875 6f 0 1 1 1 0 0 0 0 0.91250 70 0 1 1 1 0 0 0 1 0.90625 71 0 1 1 1 0 0 1 0 0.90000 72 0 1 1 1 0 0 1 1 0.89375 73 0 1 1 1 0 1 0 0 0.88750 74 0 1 1 1 0 1 0 1 0.88125 75 0 1 1 1 0 1 1 0 0.87500 76 0 1 1 1 0 1 1 1 0.86875 77 0 1 1 1 1 0 0 0 0.86250 78 0 1 1 1 1 0 0 1 0.85625 79 0 1 1 1 1 0 1 0 0.85000 7a 0 1 1 1 1 0 1 1 0.84375 7b 0 1 1 1 1 1 0 0 0.83750 7c 0 1 1 1 1 1 0 1 0.83125 7d 0 1 1 1 1 1 1 0 0.82500 7e 0 1 1 1 1 1 1 1 0.81875 7f 1 0 0 0 0 0 0 0 0.81250 80 1 0 0 0 0 0 0 1 0.80625 81 1 0 0 0 0 0 1 0 0.80000 82 1 0 0 0 0 0 1 1 0.79375 83 1 0 0 0 0 1 0 0 0.78750 84 1 0 0 0 0 1 0 1 0.78125 85 1 0 0 0 0 1 1 0 0.77500 86 1 0 0 0 0 1 1 1 0.76875 87 1 0 0 0 1 0 0 0 0.76250 88 1 0 0 0 1 0 0 1 0.75625 89
ncp5395 http://onsemi.com 19 table 2. vrm11 v id codes v id7 800 mv hex voltage (v) v id0 6.25 mv v id1 12.5 mv v id2 25 mv v id3 50 mv v id4 100 mv v id5 200 mv v id6 400 mv 1 0 0 0 1 0 1 0 0.75000 8a 1 0 0 0 1 0 1 1 0.74375 8b 1 0 0 0 1 1 0 0 0.73750 8c 1 0 0 0 1 1 0 1 0.73125 8d 1 0 0 0 1 1 1 0 0.72500 8e 1 0 0 0 1 1 1 1 0.71875 8f 1 0 0 1 0 0 0 0 0.71250 90 1 0 0 1 0 0 0 1 0.70625 91 1 0 0 1 0 0 1 0 0.70000 92 1 0 0 1 0 0 1 1 0.69375 93 1 0 0 1 0 1 0 0 0.68750 94 1 0 0 1 0 1 0 1 0.68125 95 1 0 0 1 0 1 1 0 0.67500 96 1 0 0 1 0 1 1 1 0.66875 97 1 0 0 1 1 0 0 0 0.66250 98 1 0 0 1 1 0 0 1 0.65625 99 1 0 0 1 1 0 1 0 0.65000 9a 1 0 0 1 1 0 1 1 0.64375 9b 1 0 0 1 1 1 0 0 0.63750 9c 1 0 0 1 1 1 0 1 0.63125 9d 1 0 0 1 1 1 1 0 0.62500 9e 1 0 0 1 1 1 1 1 0.61875 9f 1 0 1 0 0 0 0 0 0.61250 a0 1 0 1 0 0 0 0 1 0.60625 a1 1 0 1 0 0 0 1 0 0.60000 a2 1 0 1 0 0 0 1 1 0.59375 a3 1 0 1 0 0 1 0 0 0.58750 a4 1 0 1 0 0 1 0 1 0.58125 a5 1 0 1 0 0 1 1 0 0.57500 a6 1 0 1 0 0 1 1 1 0.56875 a7 1 0 1 0 1 0 0 0 0.56250 a8 1 0 1 0 1 0 0 1 0.55625 a9 1 0 1 0 1 0 1 0 0.55000 aa 1 0 1 0 1 0 1 1 0.54375 ab 1 0 1 0 1 1 0 0 0.53750 ac 1 0 1 0 1 1 0 1 0.53125 ad 1 0 1 0 1 1 1 0 0.52500 ae 1 0 1 0 1 1 1 1 0.51875 af 1 0 1 1 0 0 0 0 0.51250 b0 1 0 1 1 0 0 0 1 0.50625 b1 1 0 1 1 0 0 1 0 0.50000 b2 1 1 1 1 1 1 1 0 off fe 1 1 1 1 1 1 1 1 off ff
ncp5395 http://onsemi.com 20 parameter test condition typ max units vr10 dac system voltage accuracy 1.0 v < dac < 1.6 v 0. 83125 v < dac < 1.0 v ? ? 0.5 5 % mv 8. internal dac voltage is centered 19 mv below the listed voltage. for vr11.1/vr11.0/vr10 no dac offset is implemented for amd operation. v id4 400 mv v id3 200 mv v id2 100 mv v id1 50 mv v id0 25 mv v id5 12.5 mv v id6 6.25 mv voltage (v) 0 1 0 1 0 1 1 1.60000 0 1 0 1 0 1 0 1.59375 0 1 0 1 1 0 1 1.58750 0 1 0 1 1 0 0 1.58125 0 1 0 1 1 1 1 1.57500 0 1 0 1 1 1 0 1.56875 0 1 1 0 0 0 1 1.56250 0 1 1 0 0 0 0 1.55625 0 1 1 0 0 1 1 1.55000 0 1 1 0 0 1 0 1.54375 0 1 1 0 1 0 1 1.53750 0 1 1 0 1 0 0 1.53125 0 1 1 0 1 1 1 1.52500 0 1 1 0 1 1 0 1.51875 0 1 1 1 0 0 1 1.51250 0 1 1 1 0 0 0 1.50625 0 1 1 1 0 1 1 1.50000 0 1 1 1 0 1 0 1.49375 0 1 1 1 1 0 1 1.48750 0 1 1 1 1 0 0 1.48125 0 1 1 1 1 1 1 1.47500 0 1 1 1 1 1 0 1.46875 1 0 0 0 0 0 1 1.46250 1 0 0 0 0 0 0 1.45625 1 0 0 0 0 1 1 1.45000 1 0 0 0 0 1 0 1.44375 1 0 0 0 1 0 1 1.43750 1 0 0 0 1 0 0 1.43125 1 0 0 0 1 1 1 1.42500 1 0 0 0 1 1 0 1.41875 1 0 0 1 0 0 1 1.41250 1 0 0 1 0 0 0 1.40625 1 0 0 1 0 1 1 1.40000 1 0 0 1 0 1 0 1.39375 1 0 0 1 1 0 1 1.38750 1 0 0 1 1 0 0 1.38125 1 0 0 1 1 1 1 1.37500 1 0 0 1 1 1 0 1.36875 1 0 1 0 0 0 1 1.36250
ncp5395 http://onsemi.com 21 table 3. dac codes for vrm 10 v id4 400 mv v id3 200 mv v id2 100 mv v id1 50 mv v id0 25 mv v id5 12.5 mv v id6 6.25 mv voltage (v) 1 0 1 0 0 0 0 1.35625 1 0 1 0 0 1 1 1.35000 1 0 1 0 0 1 0 1.34375 1 0 1 0 1 0 1 1.33750 1 0 1 0 1 0 0 1.33125 1 0 1 0 1 1 1 1.32500 1 0 1 0 1 1 0 1.31875 1 0 1 1 0 0 1 1.31250 1 0 1 1 0 0 0 1.30625 1 0 1 1 0 1 1 1.30000 1 0 1 1 0 1 0 1.29375 1 0 1 1 1 0 1 1.28750 1 0 1 1 1 0 0 1.28125 1 0 1 1 1 1 1 1.27500 1 0 1 1 1 1 0 1.26875 1 1 0 0 0 0 1 1.26250 1 1 0 0 0 0 0 1.25625 1 1 0 0 0 1 1 1.25000 1 1 0 0 0 1 0 1.24375 1 1 0 0 1 0 1 1.23750 1 1 0 0 1 0 0 1.23125 1 1 0 0 1 1 1 1.22500 1 1 0 0 1 1 0 1.21875 1 1 0 1 0 0 1 1.21250 1 1 0 1 0 0 0 1.20625 1 1 0 1 0 1 1 1.20000 1 1 0 1 0 1 0 1.19375 1 1 0 1 1 0 1 1.18750 1 1 0 1 1 0 0 1.18125 1 1 0 1 1 1 1 1.17500 1 1 0 1 1 1 0 1.16875 1 1 1 0 0 0 1 1.16250 1 1 1 0 0 0 0 1.15625 1 1 1 0 0 1 1 1.15000 1 1 1 0 0 1 0 1.14375 1 1 1 0 1 0 1 1.13750 1 1 1 0 1 0 0 1.13125 1 1 1 0 1 1 1 1.12500 1 1 1 0 1 1 0 1.11875 1 1 1 1 0 0 1 1.11250 1 1 1 1 0 0 0 1.10625 1 1 1 1 0 1 1 1.10000 1 1 1 1 0 1 0 1.09375 1 1 1 1 1 0 1 off 1 1 1 1 1 0 0 off
ncp5395 http://onsemi.com 22 table 3. dac codes for vrm 10 v id4 400 mv voltage (v) v id6 6.25 mv v id5 12.5 mv v id0 25 mv v id1 50 mv v id2 100 mv v id3 200 mv 1 1 1 1 1 1 1 off 1 1 1 1 1 1 0 off 0 0 0 0 0 0 1 1.08750 0 0 0 0 0 0 0 1.08125 0 0 0 0 0 1 1 1.07500 0 0 0 0 0 1 0 1.06875 0 0 0 0 1 0 1 1.06250 0 0 0 0 1 0 0 1.05625 0 0 0 0 1 1 1 1.05000 0 0 0 0 1 1 0 1.04375 0 0 0 1 0 0 1 1.03750 0 0 0 1 0 0 0 1.03125 0 0 0 1 0 1 1 1.02500 0 0 0 1 0 1 0 1.01875 0 0 0 1 1 0 1 1.01250 0 0 0 1 1 0 0 1.00625 0 0 0 1 1 1 1 1.00000 0 0 0 1 1 1 0 0.99375 0 0 1 0 0 0 1 0.98750 0 0 1 0 0 0 0 0.98125 0 0 1 0 0 1 1 0.97500 0 0 1 0 0 1 0 0.96875 0 0 1 0 1 0 1 0.96250 0 0 1 0 1 0 0 0.95625 0 0 1 0 1 1 1 0.95000 0 0 1 0 1 1 0 0.94375 0 0 1 1 0 0 1 0.93750 0 0 1 1 0 0 0 0.93125 0 0 1 1 0 1 1 0.92500 0 0 1 1 0 1 0 0.91875 0 0 1 1 1 0 1 0.91250 0 0 1 1 1 0 0 0.90625 0 0 1 1 1 1 1 0.90000 0 0 1 1 1 1 0 0.89375 0 1 0 0 0 0 1 0.88750 0 1 0 0 0 0 0 0.88125 0 1 0 0 0 1 1 0.87500 0 1 0 0 0 1 0 0.86875 0 1 0 0 1 0 1 0.86250 0 1 0 0 1 0 0 0.85625 0 1 0 0 1 1 1 0.85000 0 1 0 0 1 1 0 0.84375 0 1 0 1 0 0 1 0.83750 0 1 0 1 0 0 0 0.83125
ncp5395 http://onsemi.com 23 parameter test condition min typ max units amd dac system voltage accuracy 1.0 v < dac < 1.55v 0.6 v dac < 1.0v 0.375 v < dac < 0.6v ? ? ? ? ? ? 0.5 1.0 2.0 % % % 9. note: no dac offset is implemented for amd operation. dac should be equal to the nominal v out shown in the table. table 4. amd processor 6 ? bit v id code (v id ) codes nominal v out units v id5 v id4 v id3 v id2 v id1 v id0 0 0 0 0 0 0 1.550 v 0 0 0 0 0 1 1.525 v 0 0 0 0 1 0 1.500 v 0 0 0 0 1 1 1.475 v 0 0 0 1 0 0 1.450 v 0 0 0 1 0 1 1.425 v 0 0 0 1 1 0 1.400 v 0 0 0 1 1 1 1.375 v 0 0 1 0 0 0 1.350 v 0 0 1 0 0 1 1.325 v 0 0 1 0 1 0 1.300 v 0 0 1 0 1 1 1.275 v 0 0 1 1 0 0 1.250 v 0 0 1 1 0 1 1.225 v 0 0 1 1 1 0 1.200 v 0 0 1 1 1 1 1.175 v 0 1 0 0 0 0 1.150 v 0 1 0 0 0 1 1.125 v 0 1 0 0 1 0 1.100 v 0 1 0 0 1 1 1.075 v 0 1 0 1 0 0 1.050 v 0 1 0 1 0 1 1.025 v 0 1 0 1 1 0 1.000 v 0 1 0 1 1 1 0.975 v 0 1 1 0 0 0 0.950 v 0 1 1 0 0 1 0.925 v 0 1 1 0 1 0 0.900 v 0 1 1 0 1 1 0.875 v 0 1 1 1 0 0 0.850 v 0 1 1 1 0 1 0.825 v 0 1 1 1 1 0 0.800 v 0 1 1 1 1 1 0.775 v 1 0 0 0 0 0 0.7625 v 1 0 0 0 0 1 0.7500 v
ncp5395 http://onsemi.com 24 table 4. amd processor 6 ? bit v id code (v id ) codes units nominal v out v id5 units nominal v out v id0 v id1 v id2 v id3 v id4 1 0 0 0 1 0 0.7375 v 1 0 0 0 1 1 0.7250 v 1 0 0 1 0 0 0.7125 v 1 0 0 1 0 1 0.7000 v 1 0 0 1 1 0 0.6875 v 1 0 0 1 1 1 0.6750 v 1 0 1 0 0 0 0.6625 v 1 0 1 0 0 1 0.6500 v 1 0 1 0 1 0 0.6375 v 1 0 1 0 1 1 0.6250 v 1 0 1 1 0 0 0.6125 v 1 0 1 1 0 1 0.6000 v 1 0 1 1 1 0 0.5875 v 1 0 1 1 1 1 0.5750 v 1 1 0 0 0 0 0.5625 v 1 1 0 0 0 1 0.5500 v 1 1 0 0 1 0 0.5375 v 1 1 0 0 1 1 0.5250 v 1 1 0 1 0 0 0.5125 v 1 1 0 1 0 1 0.5000 v 1 1 0 1 1 0 0.4875 v 1 1 0 1 1 1 0.4750 v 1 1 1 0 0 0 0.4625 v 1 1 1 0 0 1 0.4500 v 1 1 1 0 1 0 0.4375 v 1 1 1 0 1 1 0.4250 v 1 1 1 1 0 0 0.4125 v 1 1 1 1 0 1 0.4000 v 1 1 1 1 1 0 0.3875 v 1 1 1 1 1 1 0.3750 v
ncp5395 http://onsemi.com 25 functional descriptions general the ncp5395 dual edge modulated multiphase pwm controller is specifically designed with the necessary features for a high current cpu system. the ic consists of the following blocks: precision flexible dac, differential remote voltage sense amplifier, high performance voltage error amplifier, differential current feedback amplifiers, precision oscillator and saw ? tooth generator, and pwm comparators with hysteresis. the controller also supports power saving mode as per intel vr11.1 by accurately monitoring the current and switching between multi ? phase and single phase operations as requested by the microprocessor system. protection features include: undervoltage lockout, soft ? start, overcurrent protection, overvoltage protection, and power good monitor. precision programmable dac a precision flexible dac is provided. the dac will conform to 2 dif ferent specifications: amd or vr11.1. the vid7/amd pin is provided to determine which dac specification will be used and which soft ? start mode the part will use for power up. there are two soft ? start modes. if vid7/amd is above it?s threshold the device will soft ? start and ramp directly to the dac code present on the vid inputs. the following truth table describes the functionality: vid7/amd pin vid7 enable pin mode soft start mode above amd threshold not active amd threshol ds ramp to vid below amd threshold active vr11.1 threshol ds ramp to vboot vid inputs vid0 ? vid7 control the target regulation voltage during normal operation. in amd mode the vid capture is enabled just before soft start. in vr11 mode the vid capture is enabled at the end of the v boot waiting period. if the vid is valid the dac will track to it. if an invalid vid occurs it will be ignored for 10 s before the controller shuts down. remote sense amplifier a high performance differential amplifier is provided to accurately sense the output voltage of the regulator. the non ? inverting input should be connected to the regulator?s output voltage. the inverting input should be connected to the return line of the regulator. both connection points are intended to be at a remote point so that the most accurate reading of the output voltage can be obtained. the amplifier is configured in a very unique way. first, the gain of the amplifier is internally set to unity. second, both the inverting and non ? inverting inputs of the amplifier are summing nodes. the inverting input sums the output voltage return voltage with the dac voltage. the non ? inverting input sums the remote output voltage with a 1.3 v reference. the resulting voltage at the output of the remote sense amplifier is: v diffout v out 1.3 v v dac v outreturn this signal then goes through a standard compensation circuit and into the inverting input of the error amplifier. the non ? inverting input of the error amplifier is also connected to the 1.3 v reference. the 1.3 v reference then is subtracted out and the error signal at the comp pin of the error amplifier is as normally expected: v comp v dac v out the non ? inverting input of the remote sense amplifier is pulled low through a small current sink during a fault condition to prevent accidental charging of the regulator output. 2/3/4 phase operation the part can be configured to 2 ? , 3 ? , or 4 ? phase mode. in 2 ? or 3 ? phase mode, the internal drivers will be used. in 4 ? phase mode, an external driver must be used to drive phase 4. the ncp5359 driver is suggested to be used with the controller. the input to g4 pin will decide which phase mode the system is in operation. please refer to the application schematics for more information. high performance voltage error amplifier a high performance voltage error amplifier is provided. the error amplifier?s inverting input is vfb and its output is comp . a standard type 3 compensation circuit is used compensate the system. this involves a 3 pole, 2 zero compensation network. the comp pin is pulled to ground before soft ? start for smooth start up. differential current sense four differential amplifiers are provided to sense the output current of each phase. these current sense amplifiers sense the current through the corresponding phase. a voltage is generated across a current sense element such as an inductor or sense resistor. the sense element should be between 0.5 m and 1.5 m . it is possible to sense both negative and positive going current. the information is used to create the signal cssum and provide feedback for current sharing. precision oscillator a programmable precision oscillator is provided. this oscillator is programmed by the summed resistance of an oscillator resistor and a current limit resistor. the output voltage of this pin is used as the reference for the current limit. the oscillator frequency range is 125 khz/phase to 1000 khz/phase. the oscillator frequency is proportional to the current drawn out of the osc pin.
ncp5395 http://onsemi.com 26 pwm comparators four pwm comparators are incorporated within the ic. the non ? inverting input of the comparators is connected to the output of the error amplifier. the inverting input is connected to a summed output of the phase current and the oscillator ramp voltage with an offset. the output of the comparator generates the pwm control signals. during steady state operation, the duty cycle will center on the valley of the saw ? tooth waveform. during a transient event, the controller will operate somewhat hysteretic, with the duty cycle climbing along either the down ramp, up ramp, or both. soft ? start soft ? start is implemented internally. a digital counter steps the dac up from zero to the tar get voltage based on the predetermined rate in the spec table. there are 2 possible soft start modes: vr11 and amd. amd mode simply ramps v core from 0 v directly to the dac setting. the vr11 mode ramps dac to 1.1 v, pauses for 500 s, reads the dac setting, then ramps to the final dac setting. digital slew rate limiter / soft start block the slew rate limiter and the soft ? start block are to be implemented with a digital up/down counter controlled by an oscillator that is synchronized to vid line changes. during soft start the dac will ramp at the soft ? start rate, after soft start is complete the ramp rate will follow either the intel or the amd slew rate depending on the mode. under voltage lockouts an under voltage circuit senses the v cc input of the controller and the v ccp input of the driver. during power up the input voltage to the controller is monitored. the pwm outputs and the soft start circuit are disabled until the input voltage exceeds the threshold voltage of the comparators. hysteresis is incorporated within the comparators. the drvon is held low until v ccp reaches the start threshold during startup. if v ccp decreases below the stop threshold, the output gate will be forced low unit input voltage v ccp rises above the startup threshold. over current latch a programmable over current latch is incorporated within the ic. the oscillator pin provides the reference voltage for this pin. a resistor divider from the osc pin generates the ilim voltage. the latch is set when the current information on v droop exceeds the programmed voltage plus a 1.3 v offset. drvon is immediately set low. to recover the part must be reset by the en pin or by cycling v cc . uvlo monitor if the output voltage falls greater than 300 mv below the dac voltage for more than 5 s the uvlo comparator will trip sending the vr_rdy signal low. over voltage protection the output voltage is monitored at the input of the differential amplifier. during normal operation, if the output voltage exceeds the dac voltage by 185 mv, or 285 mv if in amd mode, the vr_rdy flag will transition low the high side gate drivers set to low, and the low side gate drivers are all brought to high until the voltage falls below the ovp threshold. if the over voltage trip 8 times the output voltage will shut down. the ovp will not shut down the controller if it occurs during soft ? start. this is to allow the controller to pull the output down to the dac voltage and start up into a pre ? charged output. v ccp power on reset ovp the v ccp power on reset ovp feature is used to protect the cpu during start up. when v ccp is higher than 3.2 v, the gate driver will monitor the switching node sw pin. if swnx pin higher than 1.9 v, the bottom gate will be forced to high for discharge of the output capacitor. this works best if the 5 volt standby is diode or?ed into v ccp with the 12 v rail. the fault mode will be latched and the drvon pin will be forced to low, unless v ccp is reduced below the uvlo threshold. power saving mode the controller is designed to allow power saving mode to maintain a maximum efficiency. when a low psi signal from microcontroller is received, the controller will keep one phase operating while shedding other phases. the active one phase will operate in diode emulation mode, minimizing power losses in light load. when the low psi signal is de ? asserted, the dropped phases will be pulled back in to be ready for heavy load. adaptive non ? overlap the non ? overlap dead time control is used to avoid shoot through damage to the power mosfets. when the pwm signal pull high, drvl will go low after a propagation delay, the controller monit ors the switching node (swn) pin voltage and the gate voltage of the mosfet to know the status of the mosfet. when the low side mosfet status is off an internal timer will delay turn on of the high?side mosfet. when the pwm pull low, gate drvh will go low after the propagation delay (tpddr vh). the time to turn off the high side mosfet is depending on the total gate charge of the high ? side mosfet. a timer will be triggered once the high side mosfet is turn off to delay the turn on the low ? side mosfet. layout guidelines layout is very important thing for design a dc ? dc converter. bootstrap capacitor and v in capacitor are most critical items, it should be plac ed as close as to the controller ic. another item is using a gnd plane. ground plane can provide a good return path for gate drives for reducing the ground noise. therefore gnd pin should be directly connected to the ground plane and close to the low ? side mosfet source pin. also, the gate drive trace should be considered. the gate drives has a high di/dt when switching, therefore a minimized gate drives trace can reduce the di/dv, raise and fall time for reduce the switching loss.
ncp5395 http://onsemi.com 27 figure 6. vr11.1 start up timing diagram 1.10 v 500 s 500 s dac setting soft ? start slew rate soft ? start slew rate drvon vout/dac vr_rdy 5 and 12 good 12 v 5 v enable 3.5 ms calibration time 12 v 1.25 v 1.25 v vid not valid vid valid 1 s ? 20 ms rise time vid captured vr11 soft ? start mode latched 1 s ? 20 ms rise time
ncp5395 http://onsemi.com 28 figure 7. amd / legacy start up timing diagram enable vid7/amd v cc 5 v 5 v v ccp 12 v amd/legacy soft start mode latched 3.5 ms calibration time 9.5 v 500 s dac setting ss slew rate 1 s ? 20 ms rise time 1 s ? 20 ms rise time v cc and v ccp uvlo drvon vout/dac vr_rdy
ncp5395 http://onsemi.com 29 package dimensions 0.15 c (a3) a a1 d2 b 1 13 24 25 48 37 2 x 2 x e2 48 x 12 36 4 x l 48 x bottom view exposed pad top view side view qfn48 case 485k ? 02 issue c 0.15 c d a b e pin 1 location 0.08 c 0.10 c e 0.10 c 0.05 c a b c 48 x notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b applies to the plated terminal and is measured abetween 0.25 and 0.30 mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 7.000 bsc d2 5.260 5.360 5.460 e 7.000 bsc e2 5.260 5.360 5.460 e 0.500 bsc k 0.200 ???? ???? l 0.300 0.400 0.500 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp5395/d the products described herein (ncp5395), may be covered by one or more of the following u.s. patents; us07057381 . there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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